The present application relates to switchable field-effect-gated power semiconductor devices which include bipolar conduction, such as IGBTs (insulated-gate bipolar transistors), Gate Turn-off thyristors GTOs and the like.
Note that the points discussed below may reflect the hindsight gained from the disclosed inventions, and are not necessarily admitted to be prior art.
MOS-gated power devices such as power DMOS transistors and IGBTs are capable of supplying large currents while withstanding voltages as high as 600 to 1500 Volts, or even more. The power dissipation of a power device is the product of the on-state voltage drop across the device times the current flow through it. The combination of high voltage across a MOS-gated power device and the high current through it may cause unwanted local heating, which can lead to device failure. While any MOS-gated device can fail if it is exposed to excessive voltage or excessive current, it is possible to increase the ability of such devices to withstand such conditions. The present application will describe such a technique below, using an n-channel IGBT as an example.
A cross section of a typical n-channel IGBT is shown in FIG. 3A. As seen in these figures, the IGBT is a four layer device. In this example, an insulated gate 120A inverts a surface (channel) portion of p-type body/emitter region 116A. (Region 116A will typically have some gradation in doping, corresponding at least to the usual combination of a shallow body implant with a deep body implant, but this gradation is well-known and is not illustrated as such.) Electrons thus emitted from source region 130A pass into drift/drain region 114 (provided by an epitaxial layer in this example) into an n+ deep drain region 112. The n+ region 112 forms a base/emitter junction with the p+ substrate 110, to thereby control hole emission, which provides hole current between collector contact 103 and emitter/source contact 102.
FIG. 3B shows a simple equivalent circuit for the device of FIG. 3A. The MOSFET transistor M1 provides the base current to the PNP bipolar transistor T1, as described above. However, this equivalent circuit is slightly oversimplified, as will now be described.
Some four layer devices, such as SCRs, display “latch-up” characteristic in their normal operation. (A latch-up condition means that the device will stay on for as long as the current is above some minimum “holding current” value, or until the device is destroyed.) However, one of the basic requirements of an IGBT is that latch-up should not occur at any time during normal operation. Both the structure of an IGBT and the processing sequence used to fabricate an IGBT are tailored to prevent latch-up from occurring.
One of the methods which may be used to prevent latch-up is understood by referring to the models of an IGBT shown in FIG. 4A. This model includes the MOS transistor M1 and bipolar transistor T1 shown in FIG. 3B, and also shows the parasitic NPN bipolar transistor T2 formed by the N+ source region 130A, the P-type body region 116A, and the N-type drain regions 112/114 of the DMOS FET present in the IGBT. If the four layer structure in the IGBT is to turn “on,” the emitter-to-base junction of the NPN bipolar transistor must become forward biased. It requires a voltage of approximately 0.6 Volts to forward bias this pn-junction. Since the emitter and base regions of this NPN bipolar are shorted at one or more locations in the IGBT, there must be a sufficiently large current flow through the resistance present in the body region to reach a body-to-source voltage (and hence, a base-to-emitter voltage) of 0.6 volts at any region in the IGBT.
FIG. 4B is based on FIG. 4A, but explicitly shows the emitter resistance in the parasitic bipolar T2. When an IGBT is conducting in normal operation, the peak base-to-emitter voltage is determined by the parasitic body resistance Rb, and the current Ib that is flowing through it, in combination with the peak emitter resistance Re, and the current Ie that is flowing through it. This voltage is justVbe=RbIb−ReIe.
From this equation, it can be seen that the presence of additional resistance in the source (which forms the emitter of the NPN bipolar transistor), provides a debiasing effect, and thereby increases the voltage that must be present across the body resistance Rb before the base-to-emitter junction of the NPN bipolar transistor becomes forward biased.